The CMOS PIXI-II ASIC

The CMOS VLSI chip has an active area of 30.7 × 24.8 mm², organized on a matrix of 512 × 476 pixels.
The chip integrates more than 350 million transistors. It is the largest ASIC of this kind ever built. Each pixel incorporates a hexagonal electrode (top metal layer) connected to a charge amplifier which feeds two discriminators and two 15-bit counters.
To reduce unavoidable variations of the DC level between the pixels, a self-calibration circuit has been implemented in each pixel. In this way a global threshold per discriminator can be applied to the entire matrix.

Matrix organization: honeycomb arrangement with a 60 μm horizontal pitch and 51.96 μm vertical pitch.Acquisition: 2 color reading (2 thresholds, 2 counters) or, alternatively, counting in one counter while reading the other one (dead-time free mode).

Senza titolo1